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PSX MODEL MOD-CHIP Design Updated for the PIC12F629

PS_2's profile picture
Published in 
Playstation
 · 25 Nov 2019

PSX MODEL MOD-CHIP Design

Version 2.01.070910.garyOPA
Based on designs by Old Crow
Updated for the PIC12F629 Chip

After 10 years of the original modchip design for the PSX machines which used the older PIC 12C508, we came across a bunch of un-modded new PS-One machines, and since we had the old source code for the PSX modchip, and the original design used the PIC 12C508 chip, which is hard or costly to get these days, and there is tons of the newer 12F629 chips around these days due to the Wii-mod.

We decided to release to the world, our quick and dirty recode of the old Classic 4-wire mod for the PSX using the 12C508 which was originally coded by the famous Old Crow (Scott Rider), and updated it to support the newer 12F629 chip.

Included in this package is the our source code, plus a complied HEX file for programming the 12F629, and a bunch of install diagrams from various sources.

(Sorry, but I can't recall the original sources for the install diagrams to give proper credit for them).

Remember when looking at the install diagrams that this is a classic 4-wire modchip design, so only use the pins marked 1 , 5 , 6 , 8 on the install diagrams.

And on the newer PSX models (9000 and Slim designs), only 3-wires were used with a link wire between 2 points.

I didn't think we would ever need to due another PSX release but here it is, if there is enough demand we will update the other source files for the newer PSX modchips, which has Stealth mode and anti-mod original playing, which this classic 4-wire version is lacking, but it is only 4 wires and were can you find original PSX discs these days which are still in working order.

We also recently had people asking for us in redoing the old drivecode mod of the Gamecube over to the PIC 12F629 chip, and we might do so within a month or two.

Have fun playing some old classic PSX games..........

-=(GaryOPA)=-

SUPPORT AND PROBLEMS


For support on this release please contact us directly:

EMAIL: opa-ltd@rogers.com
MSN: garyopa@hotmail.com
WEB: (Sorry it is offline, was http://www.o-p-a.ca)

-=(GaryOPA)=-

SPECIAL THANKS AND NOTES


Thanks for all the good support from around the world.

Be watching for NEW AND IMPROVED TECHNOLOGIES in '08 from O.P.A.

God Bless my father whom passed away this XMAS on 12/23/2007 which got me started in the computer age back in '79 with my TI99/4a which led to the foundation of OASIS PENSIVE ABACUTORS.

-=(GaryOPA)=-

Install

PSX 1000
Pin it
PSX 1000
PSX 5501
Pin it
PSX 5501
PSX 7000
Pin it
PSX 7000
PSX 7501
Pin it
PSX 7501
PSX 9000
Pin it
PSX 9000
PlayStation One
Pin it
PlayStation One

Source code


 
; PSX Model Mod-Chip design
;
; Version 2.01.070910
; Designed by garyOPA
; Developed by Phoenix 2001
; Manufacted by Oasis Pensive Abacutors
; Based on designs by Old Crow (Scott Rider)
;
; NOTES:
;
; * Re-Written to use the same chip as Wii now: 12F629
; * Instead of original code which was for the: 12C508
; * Reason for this new version of code 10 years later
;
; This version uses Microchip assembler mnemonics and the
; Microchip MPASM assembler.
;
; Chip is connected in 4-wire fashion:
;
; _______ _______
; | \/ |
; Vdd --+ 1 << >> 8 +-- Vss
; | |
; GP5/OSC1 --+ 2 7 +-- GP0
; | |
; GP4/OSC2 --+ 3 >> 6 +-- GP1
; | |
; GP3/!MCLR --+ 4 >> 5 +-- GP2/T0CKI
; | |
; +----------------+
;
; 4-wire: ">>" and "<<" indicated pins are connected.
;
; 4-Wire Operation: Be sure to set the following config options
; on the __FUSES line below: MCLRE_OFF, CP_OFF, WDT_OFF, OSC=INTRC
;
list p=12f629
include "p12f629.inc"
radix dec
errorlevel -302 ; suppress message 302 from list file;

__FUSES _MCLRE_OFF & _CP_OFF & _WDT_OFF & _INTRC_OSC_NOCLKOUT ;4-wire

cblock 0x27 ;Store variables above control registers

i ;Loop counters
j ;/
k ;/
x ;Used by delay routine
y ;/
xmit ;Transmit data holding register
index ;Index register for table lookups
mode ;Cheap counter used to toggle delay mode on original 5-wire
mode1 ;Cheap counter used to toggle delay to toggle between 249/233
;in 1msec delay, this is to allow for the errors in the 12c508
;internal RC osc. (Might not be needed on the newer 12F629)
loops ;number of times to send 3 blocks of data

endc
;
;***** VARIABLE DEFINITIONS
;
w_temp EQU 0x20 ; variable used for context saving
status_temp EQU 0x21 ; variable used for context saving
;
;**********************************************************************
;
ORG 0x000 ; processor reset vector
goto main ; go to beginning of program
;
; (12F629) = Interrupt Code (not used)
;
ORG 0x004 ; interrupt vector location
movwf w_temp ; save off current W register contents
movf STATUS,w ; move status register into W register
movwf status_temp ; save off contents of STATUS register
;
; isr code can go here or be located as a call subroutine elsewhere
;
movf status_temp,w ; retrieve copy of STATUS register
movwf STATUS ; restore pre-isr STATUS register contents
swapf w_temp,f
swapf w_temp,w ; restore pre-isr W register contents
retfie ; return from interrupt
;
; these first 4 instructions are not required if the internal oscillator is not used
;
main
bsf STATUS,RP0 ; bank 1
movlw b'10000110' ; Disable T0CKI on Pin 5
movwf OPTION_REG ; Set it!
call 0x3FF ; retrieve factory calibration value
movwf OSCCAL ; update register with factory cal value
bcf STATUS,RP0 ; set file register bank to 0
clrf GPIO ; Clear all the pins
;
; (12F629) = Goto to main PSX code
;
goto start ;Jump into main code segment
;
; Support routines
;
; dly50 -- entry for 50ms delay
; dly_ms -- entry with number of ms in w (1 to 255)
;
dly50 movlw 50 ;Enter here for a 50ms delay
dly_ms movwf x ;/

dy_0 movlw 249 ;1ms loop count on 100x series (pre-SAN batch code or 5-wire)

btfss mode1,0 ;different delay for post-SAN batch code?
movlw 233 ;yes, give it a whirl!

store_in_y
movwf y ;/

dy_1 nop ;Delay loop, default is 4 * 249 = 996 for pre-SAN
;and 4 * 233 = 932 for post-SAN

decfsz y,F
goto dy_1

dy_3 decfsz x,F ;# of 1ms delays
goto dy_0

retlw 3
;
; sendln -- send 4-byte line(s) with a 72ms marker at head of line.
; Enter with number of lines in w.
;
sendln movwf i ;Do this many lines

sl_0 movlw 72 ;Delay 72ms
call dly_ms

movlw 4 ;Do first half of line
movwf j ;/

sl_1 movf index,W ;Restore index
call lines ;Get a data byte..
movwf xmit ;..into xmit buffer
comf xmit,F ;Invert for sending
;
; Send a byte on rb.1. LSB first, 4ms/bit (250 bps) with one
; start bit and two stop bits per byte. Instead of setting and
; clearing the port bit, the port's direction is changed. The actual
; port register is set to zero, so that when the port bit is directed
; to be an output, it automatically goes low. Directing the port bit
; to be an input floats the I/O pin, and the external pullup creates
; the high. This allows open-collector operation of the port bits.
;
movlw 8 ;8 bit bytes
movwf k ;/

movlw b'11111011' ;Start bit on pin 7=1
tris GPIO

movlw 4 ;4ms bit-time
call dly_ms

sl_2 rrf xmit,F ;Get a bit..

movlw b'11111001' ;Keep port bits low when outputs
movwf GPIO ;/

btfsc STATUS,C ;High or low?
movlw b'11111011' ;Set pin 7 high via port direction control
btfss STATUS,C ;High or low?
movlw b'11111001' ;Set pin 7 low via port direction control

tris GPIO ;Set the port

movlw 4 ;Delay 4ms
call dly_ms

decfsz k,F ;Do all bits requested
goto sl_2

movlw b'11111001' ;Stop bits
tris GPIO

movlw 8 ;Two 4ms bit-times
call dly_ms
;
;
incf index,F ;Point to next
decfsz j,F
goto sl_1

decfsz i,F ;Do specified number of lines
goto sl_0

retlw 3
;
; Data block.
;
lines addwf PCL,F ;Get index into table
dt 'S','C','E','I' ;Japanese/NTSC
dt 'S','C','E','A' ;U.S./NTSC
dt 'S','C','E','E' ;European/PAL
;
; Main program loop.
;
org 0x0100

start
movlw b'11000010' ;Set TMR0 prescaler = 1:8 (f_osc=4MHz)
option ;/

movlw b'11111111' ;Make all port bits inputs initially
tris GPIO ;/

movlw 40 ;move 40 to w (# of times to loop)
movwf loops ;load register

;
; Step 1 -- approx. 50ms after reset, I/O pin 7 goes low.
;
call dly50 ;Delay 50ms

bcf GPIO,1 ;Make sure it's low
movlw b'11111101' ;Make rb.1 low via port direction
tris GPIO ;/
;
; Step 2 -- approx. 850ms later I/O pin 8 goes low.
;
step2 movlw 17 ;17 x 50ms = 850ms
movwf i ;/

s2_0 call dly50
decfsz i,F
goto s2_0 ;/

bcf GPIO,2 ;Make sure it's low
movlw b'11111001' ;Make rb.2 (and keep rb.1) low
tris GPIO ;/
;
; Step 3 -- wait approx. 314ms
;
step3 movlw 6 ;6 x 50ms = 300ms
movwf i ;/

s3_0 call dly50
decfsz i,F
goto s3_0 ;/

movlw 14 ;Final 14ms
call dly_ms
;
; Step 4 -- clock out all three datagrams on rb.1 ad infinitum.
;

step4 clrf index ;Do first line
call sendln
incf mode1,F ;Toggle delay length for 1ms delay (4-wire version)
decfsz loops,F ;decrease loop (# of times to send data)
goto step4 ;not zero, send next lot

movlw b'11111111' ;Make rb.1 input (allow normal data to go through)
tris GPIO ;/

loop_4_ever
goto loop_4_ever ;guess!
;
; (12F629) = initialize eeprom locations
;
ORG 0x2100
DE 0x00, 0x01, 0x02, 0x03
;
; (Note: do NOT overwrite factory-programmed location 0x3FF !!)
;
; That's all, folks!
;
end

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