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Dreamcast design example: G2 bus USBN9603 interface
The original article, written by jj1odm, is available at http://jj1odm.sizious.com/
spec of 'g2usb': (G2 bus USBN9603 interface version 3)
device address mapping: (byte align)
0xB4000000: USBN9603 data register
0xB4000002: USBN9603 adrs register
0xB4000001: GPIO port register (6bit GPIO port (read/write))
0xB4000003: CONTROL register
bit[7] 'irqen' enable flag (read/write)
bit[6] 'intp' status (read)
bit[5:0] GPIO direction IN:1 / OUT:0 (read/write)
interrupt: use /IRQA
device access time: 160nSEC (use /BTA /BTB control)
device enable/disable logic: (for internal reset)
enable: write word MAGIC code
disable: write long word MAGIC code
magic code: 0x4b46 (my initial name 'KF')
g2usb circuit
cpld internal ciucuit
g2usb3.v
// $$$ : g2usb3.v -- G2 bus < => USBN9603 (mode 0) interface version 3.
//
// used circuit: g2usbn9603_3.gif
// used device: XC9572XL-VQ44 (Xilinx)
// last update: 2006/10/30
//
// device mapping:
// base address + 0: USBN9603 data register (lower byte mapping)
// base address + 2: USBN9603 adrs register (lower byte mapping)
// base address + 1: GPIO port register (upper byte mapping)
// base address + 3: CONTROL register (upper byte mapping)
// CONTROL register:
// bit[7] 'irqen' enable flag (read/write)
// bit[6] 'intp' status (read)
// bit[5:0] GPIO direction IN:1 / OUT:0 (read/write)
//
// history:
// version 3: (circuit: g2usbn9603_3.gif)
// use G2 bus /BTA /BTB signal. (bus access time control)
// USBN9603 data bus to direct G2 bus (not enough terminal 'XC9572XL-VQ44')
// add GPIO port P5 - P0 (6bit)
// add device enable/disable logic (use magic code)
// enable: write word MAGIC_CODE
// disable: write long word MAGIC_CODE
// add internal reset (use 'magic_valid' flag)
//
// version 2: (circuit: g2usbn9603_2.gif)
// change G2 bus signal name (dir => lben / den => uben)
// device address mapping: from long word align to byte align
// device access: from word access to byte access
//
// date 2006/10/19 designed by jj1odm
`timescale 1ns / 1ps
module g2usb3(
input clk, // G2 bus system clock (25MHz)
input aen, // G2 bus address enable (active low)
input lben, // G2 bus direction and lower byte enable (active low) [change name: dir => lben]
input uben, // G2 bus upper byte enable (active low) [change name: den => uben]
inout [15:0] ad, // G2 bus address/data multiplexed bus (16 bit)
output btan, // G2 bus bus termination A (active low)
output btbn, // G2 bus bus termination B (active low)
output irqn, // G2 bus interrupt (open drain active low)
output csn, // USBN9603 chip select (active low)
output a0, // USBN9603 a0 address (data/adrs register select)
output rdn, // USBN9603 read strobe (active low)
output wrn, // USBN9603 write strobe (active low)
input intp, // USBN9603 interrupt (active high)
inout [5:0] p // GPIO port (6 bit)
);
parameter IOBASE_HIGH = 13'h1400; // I/O base high word address
parameter IOBASE_LOW = 14'b00000000000000; // I/O base low word address
parameter MAGIC_CODE = 16'h4b46; // magic code (my initial name 'KF')
parameter G2_IDLE = 2'b00; // G2 bus idle state
parameter G2_HI_ADDRESS = 2'b01; // G2 bus high address state
parameter G2_DATA = 2'b11; // G2 bus data state
parameter G2_END = 2'b10; // G2 bus end state
parameter ACCESS_WIDTH = 0; // bus access width (ACCESS_WIDTH * 40nSEC) + 160nSEC
reg magic_valid = 1'b0; // magic code valid flag register (init 0)
reg [1:0] g2bus_state = G2_IDLE; // G2 bus state machine register (init G2_IDLE state)
reg aen_old = 1'b1; // G2 bus cycle detect register (init '1')
reg [3:0] wait_cnt = 4'b0000; // G2 bus wait counter (init 0)
reg bus_end = 1'b1; // bus end flag (active low)
reg [15:0] g2reg; // for g2 bus tri-state logic
reg adrs; // 'AD1' address latch register (1bit)
reg direction; // direction latch register
reg irqen = 1'b0; // interrupt enable register (initial disable)
reg [5:0] gpioreg = 6'b000000; // GPIO output port register (init 0)
reg [5:0] gpiodir = 6'b111111; // GPIO direction control register (init all input)
wire bus_valid; // bus cycle valid flag node
wire bus_valid_2; // bus cycle valid 2 flag node
wire [7:0] control_node; // control register node
// control register node bit assign
assign control_node[7] = irqen; // interrupt enable (bit 7)
assign control_node[6] = intp; // assign 'intp' to (bit 6)
assign control_node[5:0] = gpiodir; // bit [5:0] GPIO direction register
// GPIO port assign
assign p[5] = gpiodir[5] ? 1'bz : gpioreg[5]; // P5
assign p[4] = gpiodir[4] ? 1'bz : gpioreg[4]; // P4
assign p[3] = gpiodir[3] ? 1'bz : gpioreg[3]; // P3
assign p[2] = gpiodir[2] ? 1'bz : gpioreg[2]; // P2
assign p[1] = gpiodir[1] ? 1'bz : gpioreg[1]; // P1
assign p[0] = gpiodir[0] ? 1'bz : gpioreg[0]; // P0
// 'irqn' siganl assign
assign irqn = (intp & irqen) ? 1'b0 : 1'bz; // assign 'irqn'
// G2 bus termination control A/B (for byte access)
assign btan = g2bus_state == G2_END ? bus_end : 1'bz;
assign btbn = g2bus_state == G2_END ? bus_end : 1'bz;
// USBN9603 interface node (lower byte access)
assign bus_valid = magic_valid & (g2bus_state == G2_DATA | g2bus_state == G2_END); // bus valid flag
assign bus_valid_2 = g2bus_state == G2_DATA | g2bus_state == G2_END; // bus valid 2 flag
assign csn = ~(~lben & uben & bus_valid); // USBN9603 'csn'
assign a0 = adrs; // USBN9603 'a0'
assign rdn = ~(direction & ~lben & uben & bus_valid); // USBN9603 'rdn'
assign wrn = ~(~direction & ~lben & uben & bus_valid); // USBN9603 'wrn'
// G2 bus tri-state buffer & etc registers logic (upper byte access)
assign ad = g2reg;
always @(magic_valid or bus_valid_2 or uben or lben or direction or adrs or control_node or p or ad) begin
if (magic_valid) begin
if (bus_valid_2 & ~uben & lben) begin // upper byte access
if (direction) begin // read
g2reg[7:0] < = 8'hzz;
if (adrs) g2reg[15:8] < = control_node; // read control register
else g2reg[15:8] < = {2'b00, p}; // read GPIO port (msb 2bit always '0')
end
else begin // write
g2reg < = 16'hzzzz;
if (adrs) begin // control register
irqen < = ad[15]; // write irqen bit (bit 7)
gpiodir < = ad[13:8]; // write GPIO direction register
end
else gpioreg < = ad[13:8]; // write GPIO port register
end
end
else g2reg < = 16'hzzzz;
end
else begin // internal reset: magic_valid == 0 then reset etc regs
g2reg < = 16'hzzzz;
irqen < = 1'b0;
gpiodir < = 6'b111111;
gpioreg < = 6'b000000;
end
end
// G2 bus state machine (ignore: not this device or long word access)
always @(posedge clk) begin
aen_old < = aen; // for negtive edge detect 'aen'
// idle state
if (g2bus_state == G2_IDLE) begin
// negtive edge detect 'aen' & equal IOBASE_LOW
if (~aen & aen_old & ad[15:2] == IOBASE_LOW) begin
adrs < = ad[1]; // 'AD1' (low word address) latch
direction < = lben; // direcion latch
wait_cnt < = 4'b0000; // init wait count
bus_end < = 1'b1; // init bus end flag
g2bus_state < = G2_HI_ADDRESS; // next state
end
end
// high address state
if (g2bus_state == G2_HI_ADDRESS) begin
if (ad[12:0] == IOBASE_HIGH) g2bus_state < = G2_DATA; // this device then next state
else g2bus_state < = G2_IDLE; // else return idle state
end
// data state
if (g2bus_state == G2_DATA) begin
if (~magic_valid) begin
if (~adrs & ~uben & ~lben & aen & ~direction & ad == MAGIC_CODE) begin // IOBASE write MAGIC_CODE (word) then
magic_valid < = 1'b1; // set 'magic_valid' flag (device enable)
end
g2bus_state < = G2_IDLE; // return idle state
end
else begin // magic_valid flag on then valid bus cycle
if (~aen) begin // long word access
if (~adrs & ~uben & ~lben & ~direction & ad == MAGIC_CODE) begin // IOBASE write MAGIC_CODE (long word) then
magic_valid < = 1'b0; // clear 'magic_valid' flag (device disable)
end
g2bus_state < = G2_IDLE; // return idle state
end
else begin // normal bus access
wait_cnt < = wait_cnt + 4'b0001;
if (wait_cnt == ACCESS_WIDTH) begin // check bus wait count
bus_end < = 1'b0; // bus_end active low
g2bus_state < = G2_END; // next state
end
end
end
end
// bus end state (for bus end pulse)
if (g2bus_state == G2_END) begin
bus_end < = 1'b1; // 1 clock bus_end high
if (bus_end) begin // for fast rising edge (guard of hi-z)
g2bus_state < = G2_IDLE; // return idle state
end
end
end
endmodule
// end of : g2usb3.v
g2usb3.ucf
// Template UCF file created by the Project Navigator
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "a0" LOC = "P22" ;
NET "ad< 0>" LOC = "P30" ;
NET "ad< 10>" LOC = "P41" ;
NET "ad< 11>" LOC = "P42" ;
NET "ad< 12>" LOC = "P43" ;
NET "ad< 13>" LOC = "P44" ;
NET "ad< 14>" LOC = "P2" ;
NET "ad< 15>" LOC = "P3" ;
NET "ad< 1>" LOC = "P31" ;
NET "ad< 2>" LOC = "P32" ;
NET "ad< 3>" LOC = "P33" ;
NET "ad< 4>" LOC = "P34" ;
NET "ad< 5>" LOC = "P36" ;
NET "ad< 6>" LOC = "P37" ;
NET "ad< 7>" LOC = "P38" ;
NET "ad< 8>" LOC = "P39" ;
NET "ad< 9>" LOC = "P40" ;
NET "aen" LOC = "P5" ;
NET "clk" LOC = "P1" ;
NET "csn" LOC = "P29" ;
NET "btbn" LOC = "P21" ;
NET "btan" LOC = "P20" ;
NET "p< 0>" LOC = "P19" ;
NET "p< 1>" LOC = "P18" ;
NET "p< 2>" LOC = "P16" ;
NET "p< 3>" LOC = "P14" ;
NET "p< 4>" LOC = "P13" ;
NET "p< 5>" LOC = "P12" ;
NET "uben" LOC = "P6" ;
NET "lben" LOC = "P7" ;
NET "intp" LOC = "P23" ;
NET "irqn" LOC = "P8" ;
NET "rdn" LOC = "P28" ;
NET "wrn" LOC = "P27" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
cpld fuse data
Programmer Jedec Bit Map
Date Extracted: Fri Nov 10 01:26:07 2006
QF46656*
QP44*
QV0*
F0*
X0*
J0 0*
N DEVICE XC9572XL-5-VQ44*
N PPMAP 24 1*
N PPMAP 46 12*
N PPMAP 49 13*
N PPMAP 50 14*
N PPMAP 52 16*
N PPMAP 59 18*
N PPMAP 62 19*
N PPMAP 26 2*
N PPMAP 63 20*
N PPMAP 65 21*
N PPMAP 68 22*
N PPMAP 72 23*
N PPMAP 82 27*
N PPMAP 83 28*
N PPMAP 87 29*
N PPMAP 27 3*
N PPMAP 88 30*
N PPMAP 89 31*
N PPMAP 90 32*
N PPMAP 92 33*
N PPMAP 3 34*
N PPMAP 7 36*
N PPMAP 9 37*
N PPMAP 10 38*
N PPMAP 11 39*
N PPMAP 12 40*
N PPMAP 13 41*
N PPMAP 15 42*
N PPMAP 20 43*
N PPMAP 21 44*
N PPMAP 29 5*
N PPMAP 31 6*
N PPMAP 33 7*
N PPMAP 38 8*
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L0045424 00000000 00000000 00000000 00000000*
L0045456 00000000 00000000 00000000 00000000*
L0045488 00000000 00000000 00000000 00000000*
L0045520 00000000 00000000 00000000 00000000*
L0045552 00000000 00000000 00000000 00000000*
L0045584 00000000 00000000 00000000 00000000*
L0045616 00000000 00000000 00000000 00000000*
L0045648 000000 000000 000000 000000*
L0045672 000000 000000 000000 000000*
L0045696 000000 000000 000000 000000*
L0045720 000000 000000 000000 000000*
L0045744 000000 000000 000000 000000*
L0045768 000000 000000 000000 000000*
L0045792 00000000 00000000 00000000 00000000*
L0045824 00000000 00000000 00000000 00000000*
L0045856 00000000 00000000 00000000 00000000*
L0045888 00000000 00000000 00000000 00000000*
L0045920 00000000 00000000 00000000 00000000*
L0045952 00000000 00000000 00000000 00000000*
L0045984 00000000 00000000 00000000 10000000*
L0046016 00000000 00000000 00000000 00000000*
L0046048 00000000 00000000 00000000 00000000*
L0046080 000000 000000 000000 000000*
L0046104 000000 000000 000000 000000*
L0046128 000000 000000 000000 000000*
L0046152 000000 000000 000000 000000*
L0046176 000000 000000 000000 000000*
L0046200 000000 000000 000000 000000*
L0046224 00000000 00000000 00000000 00000000*
L0046256 00000000 00000000 00000000 10000000*
L0046288 00000000 00000000 00000000 10000000*
L0046320 00000000 00000000 00000000 00000000*
L0046352 00000000 00000000 00000000 00000000*
L0046384 10000000 00000000 00000000 00000000*
L0046416 00000000 00000000 00000000 00000000*
L0046448 00000000 00000000 00000000 00000000*
L0046480 00000000 00000000 00000000 00000000*
L0046512 000000 000000 000000 000000*
L0046536 000000 000000 000000 000000*
L0046560 000000 000000 000000 000001*
L0046584 000000 000000 000000 000001*
L0046608 000000 000000 000000 000001*
L0046632 000000 000000 000000 000001*
C3511*
187B
usb device sample soft (usb wheel mouse)
S00F000064636D6F7573652E7372656325
S3158C0100000CD00BD11B202B4009000CD0189112203F
S3158C01001009D000E10900090009000900090009005D
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S3158C0100F4FC88F38908880F8B0378806201E1FD788B
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S3158C0104D4F668464BC800F606881308020001090023
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GPIO sample soft (LCD module control)
// $$$ : lcd.c -- GPIO port LCD control test program. by jj1odm
//
// GPIO port bit assign: (LCD : 4 bit bus)
// P5 : LCD E
// P4 : LCD RS
// P3 : LCD D7
// P2 : LCD D6
// P1 : LCD D5
// P0 : LCD D4
// (GND : LCD R/W)
// (GND : LCD contrast)
// (+5V : LCD VDD)
// (GND : LCD VSS)
typedef unsigned char uchar;
typedef unsigned short ushort;
typedef unsigned long ulong;
#define G2USB_BASE 0xb4000000 // G2USB base address
#define G2USB_MAGIC_CODE 0x4b46 // G2USB magic code (my name "KF")
#define USBN9603_DATA (G2USB_BASE + 0) // USBN9603 data register
#define USBN9603_ADRS (G2USB_BASE + 2) // USBN9603 address register
#define GPIO_REG (G2USB_BASE + 1) // GPIO port register
#define CONTROL_REG (G2USB_BASE + 3) // control register
#define LCD_E 0x20
#define LCD_RS 0x10
#define LCD_FUNC_8BIT 0x30 // LCD function 8bit mode
#define LCD_FUNC_4BIT 0x20 // LCD function 4bit mode
#define LCD_CLR_CMD 0x01 // LCD clear command
#define LCD_DDR_CMD 0x80 // LCD DD address command
#define lcd_putc(c) lcd_data(c)
void delay_u(int usec)
{
while (usec--) (void)*((volatile ulong *)G2USB_BASE);
}
void delay_m(int msec)
{
msec = msec * 770;
while (msec--) (void)*((volatile ulong *)G2USB_BASE);
}
void lcd_cw(uchar cmd)
{
uchar dat;
dat = (cmd & 0xf0) >> 4; // RS = OFF (command)
*((volatile uchar *)GPIO_REG) = dat; //
delay_u(1);
*((volatile uchar *)GPIO_REG) = dat|LCD_E; // LCD E ON
delay_u(2);
*((volatile uchar *)GPIO_REG) = dat; // LCD E OFF
delay_u(1);
}
void lcd_dw(uchar data)
{
uchar dat;
dat = ((data & 0xf0) >> 4) | LCD_RS; // RS = ON (data)
*((volatile uchar *)GPIO_REG) = dat;
delay_u(1);
*((volatile uchar *)GPIO_REG) = dat|LCD_E; // LCD E ON
delay_u(2);
*((volatile uchar *)GPIO_REG) = dat; // LCD E OFF
delay_u(1);
}
void lcd_cmd(uchar cmd)
{
lcd_cw(cmd);
lcd_cw(cmd < < 4);
delay_u(50);
}
void lcd_data(uchar data)
{
lcd_dw(data);
lcd_dw(data < < 4);
delay_u(50);
}
void lcd_init(void)
{
delay_m(15);
lcd_cw(LCD_FUNC_8BIT);
delay_m(5);
lcd_cw(LCD_FUNC_8BIT);
delay_u(100);
lcd_cw(LCD_FUNC_8BIT);
delay_u(100);
lcd_cw(LCD_FUNC_4BIT);
delay_u(100);
lcd_cmd(0x2E);
lcd_cmd(0x08);
lcd_cmd(0x0D);
lcd_cmd(0x06);
}
void gpio_init(void)
{
*((volatile ushort *)G2USB_BASE) = G2USB_MAGIC_CODE; // device enable
*((volatile uchar *)CONTROL_REG) = 0; // GPIO direction all output & interrrupt disable
*((volatile uchar *)GPIO_REG) = 0; // GPIO port init 0
}
void lcd_clr(void)
{
lcd_cmd(LCD_CLR_CMD);
delay_m(5);
}
void lcd_cur(int x, int y)
{
lcd_cmd(LCD_DDR_CMD | x | (y == 0 ? 0 : 0x40));
}
void lcd_puts(register uchar *s)
{
while (*s) lcd_putc(*s++);
}
void atexit() {}
int main()
{
gpio_init();
lcd_init();
lcd_clr();
lcd_cur(0, 0);
lcd_puts("G2USB(V3) GPIO test");
lcd_cur(0, 1);
lcd_puts("LCD drive by jj1odm");
for (;;)
;
}
// end of : lcd.c
GPIO sample soft (N64 joypad control)
// $$$ : n64joypad.c -- N64 joypad control test program. by jj1odm
//
// GPIO port bit assign:
// P0 : N64 joypad data
// (+3.3V : N64 joypad VCC)
// (GND : N64 joypad GND)
#include "sci.h"
typedef unsigned char uchar;
typedef unsigned short ushort;
typedef unsigned long ulong;
#define G2USB_BASE 0xb4000000 // G2USB base address
#define G2USB_MAGIC_CODE 0x4b46 // G2USB magic code (my name "KF")
#define USBN9603_DATA (G2USB_BASE + 0) // USBN9603 data register
#define USBN9603_ADRS (G2USB_BASE + 2) // USBN9603 address register
#define GPIO_REG (G2USB_BASE + 1) // GPIO port register
#define CONTROL_REG (G2USB_BASE + 3) // control register
#define P0 0
#define P1 1
#define P2 2
#define P3 3
#define P4 4
#define P5 5
#define OK 0x00000000
#define PORT_ERR 0x00000001
#define TIMEOUT_ERR 0x00000002
#define STOPBIT_ERR 0x00000004
#define TIMEOUT 1000
#define N64_GET_JOYPAD_CMD 0x01
static uchar gpio_port_work;
static uchar n64joypad_data;
static int joypad_err;
static void delay_u(int usec)
{
while (usec--) (void)*((volatile ulong *)G2USB_BASE);
}
static void delay_m(int msec)
{
msec = msec * 770;
while (msec--) (void)*((volatile ulong *)G2USB_BASE);
}
static void delay1u(void) // 1uSEC delay
{
int i;
for (i = 0; i < 46; i++)
;
}
static void delay1u5(void) // 1.5uSEC delay
{
int i;
for (i = 0; i < 69; i++)
;
}
static void n64_cmd(uchar cmd)
{
int i;
gpio_port_work |= n64joypad_data; // port on
*((volatile uchar *)GPIO_REG) = gpio_port_work; //
*((volatile uchar *)CONTROL_REG) &= ~n64joypad_data;// direction output
for (i = 0; i < 8; i++) {
if (cmd & 0x80) { // '1' then '_---'
gpio_port_work &= ~n64joypad_data;
*((volatile uchar *)GPIO_REG) = gpio_port_work;
delay1u();
gpio_port_work |= n64joypad_data;
*((volatile uchar *)GPIO_REG) = gpio_port_work;
delay1u();
delay1u();
delay1u();
} else { // '0' then '___-'
gpio_port_work &= ~n64joypad_data;
*((volatile uchar *)GPIO_REG) = gpio_port_work;
delay1u();
delay1u();
delay1u();
gpio_port_work |= n64joypad_data;
*((volatile uchar *)GPIO_REG) = gpio_port_work;
delay1u();
}
cmd < < = 1;
}
gpio_port_work &= ~n64joypad_data;
*((volatile uchar *)GPIO_REG) = gpio_port_work; // stop bit '__--'
delay1u(); //
delay1u(); //
gpio_port_work |= n64joypad_data; //
*((volatile uchar *)GPIO_REG) = gpio_port_work; //
*((volatile uchar *)CONTROL_REG) |= n64joypad_data; // direction input
}
static ulong get_bit(void)
{
int n = 0;
ulong r;
for (n = 0;; n++) { // wait low
if (!(*((volatile uchar *)GPIO_REG) & n64joypad_data)) break;
if (n >= TIMEOUT) return(-1);
}
delay1u5();
r = *((volatile uchar *)GPIO_REG) & n64joypad_data ? 1 : 0;
for (n = 0;; n++) { //wait high
if (*((volatile uchar *)GPIO_REG) & n64joypad_data) break;
if (n >= TIMEOUT) return(-1);
}
return(r);
}
static ulong get_n64_joypad(void)
{
int i;
ulong c, r = 0;
joypad_err = OK;
for (i = 0; i < 32; i++) {
r < < = 1;
if ((c = get_bit()) == -1) {
joypad_err = TIMEOUT_ERR;
delay_u(150);
return(r);
}
r |= c & 1;
}
if ((c = get_bit()) == -1) {
joypad_err = TIMEOUT_ERR | STOPBIT_ERR;
delay_u(20);
}
return(r);
}
ulong read_n64_joypad(int port, int *err)
{
ulong r;
if (port < P0 || port > P5) {
joypad_err = PORT_ERR;
} else {
n64joypad_data = (uchar)(1 < < port);
n64_cmd(N64_GET_JOYPAD_CMD);
r = get_n64_joypad();
}
if (joypad_err != OK) r = 0;
*err = joypad_err;
return(r);
}
void test_loop(void)
{
for (;;) {
*((volatile uchar *)GPIO_REG) = 0;
delay1u();
*((volatile uchar *)GPIO_REG) = 1;
delay1u();
}
}
void gpio_init(void)
{
*((volatile ushort *)G2USB_BASE) = G2USB_MAGIC_CODE;// device enable
*((volatile uchar *)CONTROL_REG) = 0x3f; // GPIO direction all intput & interrrupt disable
gpio_port_work = 0; // GPIO port init
*((volatile uchar *)GPIO_REG) = gpio_port_work; //
}
void atexit() {}
void tostr(char *s, ulong val)
{
int i;
*s++ = '\r';
for (i = 0; i < 32; i++) {
if (i && (i % 8) == 0) *s++ =' ';
*s++ = val & 0x80000000 ? '1' : '0';
val < < = 1;
}
*s = 0;
}
int main()
{
ulong r;
int err;
char buf[80];
sci_init(57600);
gpio_init();
for (;;) {
r = read_n64_joypad(P0, &err);
if ((r & 0x80000000)) break;
tostr(buf, r);
sci_sendstr(buf);
sci_flush();
delay_m(16);
}
sci_sendstr("\n\r");
sci_flush();
}
// end of : n64joypad.c
reference picture
about USBN9603:
USBN9603 is a slave controller of USB.
(It is not possible to use it as a host controller.)
example of USB device:
USBN9603 slave controller SPI/parallel interface
SL811HST host/slave controller parallel interface
MAX3421 host/slave controller SPI interface
(The bus interface of SL811HST is also almost the same as the case of USBN9603.)
