Dreamcast technical

Dreamcast main memory subsystem v1.2, 2001-03-15 Note: Table 3.2.1 contains the essential timing figures. Remember that the cycles given are buscycles (100MHz), not SH4 core cycles! Table of Contents 0. Introduction 0.1 Quickstart 1. Dreamcast main memory configuration 2. SDRAM operation 2.1 Overview. Figure 2.1.1: Model of an SDRAM chip 2.2 Commands 2.3 Read / write access 2.4 Aborting and pipelining bus transactions 3. SDRAM in the Dreamcast 3.1 Access philosophy 3.2 Access timing in RASDown mode Table 3.2.1: Common access timings Figure 3.2.1: CPU burst read, no row active Figure 3.2.2: CPU burst read, row hit Figure 3.2.3: CPU bur...

A word from BlackAura This tutorial was written by IM(r)eaper, and covers using SDL for 2D graphics on the Dreamcast, and on any other system that supports SDL. I have corrected a couple of bits of spelling or grammar, but otherwise it's the same as the version posted in the DC Emulation and IMR Technology forums. And now, over to IM(r)eaper... Introduction In reading BlackAura's 2D for KOS, I have been thinking of writting a version as close as I can to what his teaches. This will be for SDL, and thats some thing I can write a tutorial for. The big plus is you can test this on the PC as well, unlike KOS, where if you don't have a Dreamc...

Introduction This tutorial was written by BlueCrab, and was converted to HTML by me (BlackAura). It's covers using the PowerVR hardware of the Dreamcast to do pretty much the same thing as my first four 2D graphics tutorials, so it might be a good idea to have a look at those first - much of it, especially in the first part about Dreamcast video modes, still applies when using the PowerVR hardware. I also added a couple of comments to clarify the usage of some of the code. Those notes are written in italics. Anyway, over to BlueCrab... Initialization Just a few little differences between regular, and PVR init. First of all, set your vide...

Dreamcast Serial Port: back-side -------------------------------------------------------------- | | | video serial | | | | | | | | B1 B10 | | | -------------------------------------------------------------- b1 +5V b2 b3 GND b4 RX2 b5 TX2 b6 RTS b7 CTS b8 b9 b10 +3,3V Dreamcast Parallel Port Addr: 0xb4000000 -> Area5 1 5V 2 5V 3 5V 4 5V 5 ? 6 ? 7 ? 8 ? 9 ? 10 GND 11 GND 12 GND 13 ? 14 /CE? /RD FRAME? 15 /RDY 16 /CS? 17 3,3V 18 3,3V 19 3,3V 20 ? 21 /BS ; /AEN 22 ? 23 GND 24 GND 25 AD15 26 AD14 27 AD13 28 AD12 29 AD11 30 AD10 31 AD9 32 AD8 33 AD7 34 AD6 35 AD5 36 AD4 37 AD3 38 AD2 39 AD1 40 D0 41 AGND ? 42 AGND ? 43 CLK 44 GND 45 GND 46 ? 4...

Guide to the PowerVR-chip of the Dreamcast by Lars Olsson v0.40, 2001-Aug-18 a05f8000: (id) +------+ | 31-0 | | id | +------+ id: 0x17fd11db: Set5.xx development box or consumer machine others: Set4 delopment box or others a05f8004: (revision) +----------------------+ | 31-8 | 7-4 | 3-0 | | n/a | major | minor | +----------------------+ major.minor: 0.1: Set5.16 development box (?) >= 1.1: Set5.2x development box or consumer machine a05f8008: (reset) +---------------------------------+ | 31-3 | 2 | 1 | 0 | | n/a | buss | render | transfer | +---------------------------------+ bus: 0: normal 1: reset VRAM bus render: 0: normal 1: reset re...

Reference guide to the TA registers This is a continuation of my previous text 'ta-into.txt' which described how to construct TA lists. This document provides information about the TA registers. Thanks must go to Dan Potter and Sergio Moreira for very helpful contributions. reach me at: jlo@ludd.luth.se Introduction The TA works by receiving lists containing vertex information. Unlike most architectures, the PVR core uses a technique known as deferred rendering whereby no polygons are rendered until the whole scene has been setup. The advantage is that the PVR will only render those polygons that are actually visible thus creating a very...

Some notes on the Tiling Accelerator: update: filled in some stuff about blending modes and clarified and corrected some stuff. 2001-08-18 update: filled in some stuff on sprites and modifier volumes Note: There are a few different incarnations of the PowerVR-chipset and they are not completely compatible with each other. Unfortunately previous versions of this document contained information only relevant to the older CLX1 chipset whereas the Dreamcast uses a chipset similar to the newer CLX2. Information has now been updated and where differences exist they are noted with the tags CLX1 and CLX2. [This note was mistakenly excluded from t...